Referenzmarkierungsstruktur zur Justierung der Ausrichtung von unfertigen Topographien von integrierten Halbleiterschaltungen in Bezug auf aufeinanderfolgende Masken.

摘要

A reference mark (20) structure for guiding the alignment and true superposition of unfinished topographies of semiconductor integrated circuits (3) to respective masks (21) during the manufacturing process of such circuits, consists of a substantially step-like uneveness produced on the surface of a silicon wafer (2) affected by said topography and comprises first (7) and second (10) layers of polycrystalline silicon overlying each other and being covered with a layer (11) of metallic silicide. Advantageously, said layers (7,10,11) are formed over a field oxide surface region (5), and the resulting structure can be readily identified by means of a laser beam optical scanner apparatus (15).