128 Gigabit fibre channel physical architecture

摘要

The PCS and FEC layers are combined into a single layer and the number of lanes is set at four lanes. The combination allows removal of many modules as compared to a serial arrangement of a PCS layer and an FEC layer. The reduction in the number of lanes, as compared to 100 Gbps Ethernet, provides a further simplification or cost reduction by further reducing the needed gates of an ASIC to perform the functions. Changing the lanes in the FEC layer necessitates changing the alignment marker structure. In the preferred embodiment a lane zero marker is used as the first alignment marker in each lane to allow rapid sync. A second alignment marker indicating the particular lane follows the first alignment marker.

主权项

1. A physical layer network interface link apparatus comprising:
a combined physical coding sublayer (PCS) and Reed-Solomon (RS) forward error correction (FEC) sublayer module, said combined PCS and RS FEC module developed on a single chip, wherein said combined PCS and RS FEC module includes:
a media access control (MAC) interface for connection to a MAC layer providing or receiving a stream of 64 bit blocks;a physical media attachment (PMA) interface for connection to a PMA layer utilizing four lanes;an RS FEC encoder module; andan RS FEC decoder module, and wherein said combined PCS and RS FEC module operates using only four lanes.