发明名称 DATA TRANSMISSION CIRCUIT AND BROADCAST RECEIVER
摘要 <P>PROBLEM TO BE SOLVED: To provide a data transmission circuit which can prevent such a situation that clock data of a CPU is lost as a result of momentary power failure or the like. <P>SOLUTION: The main CPU 3 counts the clock data in a power-on state. The main CPU 3 transfers the clock data to a sub CPU 8 since power supply to the main CPU 3 is stopped by an OFF state of the second power supply circuit 12 in a standby state. When the clock data of the main CPU 3 is lost as a result of the momentary power failure or the like, the main CPU 3 transmits the data indicating 'clock data is not set' to the sub CPU 8 during shifting to the standby. When the sub CPU 8 receives the data indicating 'clock data is not set' in a state of holding the clock data, the sub CPU neglects the data and continues to count on the basis of the clock data held by itself. <P>COPYRIGHT: (C)2004,JPO
申请公布号 JP2003324667(A) 申请公布日期 2003.11.14
申请号 JP20020132429 申请日期 2002.05.08
申请人 SANYO ELECTRIC CO LTD 发明人 MATSUYAMA HIDETO
分类号 G04G99/00;H04N5/44;H04N5/63 主分类号 G04G99/00
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