GATE DRIVER CIRCUIT BASING ON IGZO PROCESS

摘要

The present invention provides a gate driver circuit basing on IGZO process, comprising GOAs in cascade connection comprising a Nth-stage GOA, wherein the Nth-stage GOA further comprising a pull-up control part 100, a pull-up part 200, a transfer part 300, a pull-down part 400, a pull-down holding part 500, a boost part 600, a first negative supply VSS1, a second negative supply VSS2, a third negative supply VSS3, which are three gradually decreasing negative supplies and pull down an output terminal G(N), a first node Q(N), a second node P(N), and a driving single ST(N) to prevent the electrical leakage of TFTs effectively. And channels of the TFT switches of the gate driver circuit basing on the IGZO process are oxide semiconductor channels.

主权项

1. A gate driver circuit basing on IGZO process, comprising:
GOAs in cascade connection comprising a Nth-stage GOA, wherein the N is a positive integer, wherein the Nth-stage GOA further comprising: a pull-up part having a first transistor, wherein a gate of the first transistor electrically connects a first node, a source of the first transistor electrically connects a first clock signal, a drain of first transistor electrically connects an output terminal, wherein the first transistor is used for outputting signals on the output terminal according to the first clock signal; a transfer part having a second transistor, wherein a gate of the second transistor electrically connects the first node, a source of the second transistor electrically connects the first clock signal, a drain of the second transistor electrically connects a driving signal terminal, wherein the second transistor is used for outputting the diving signal from the driving signal terminal according to the first clock signal; a pull-up control part having a third transistor, wherein a gate of the third transistor electrically connects the driving signal terminal of a N−1th-stage GOA, a source of the third transistor electrically connects the output terminal of the N−1th-stage GOA, the drain of the third transistor electrically connects the first node, wherein the third transistor is used for conducting the pull-up part according to the driving signal from the driving signal terminal; a pull-down holding part having a first pull-down holding circuit and a second pull-down circuit, wherein the first pull-down holding circuit further comprising a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a eighth transistor, a ninth transistor, and a tenth transistor; wherein a gate of the fourth transistor electrically connects the first clock signal, a source of the fourth transistor electrically also connects the first clock signal, a drain of fourth transistor electrically connects a second node, a gate of the fifth transistor electrically connects the driving signal terminal, a source of the fifth transistor electrically connects the second node, a drain of the fifth transistor electrically connects a second negative supply, a gate of the sixth transistor electrically connects the driving signal terminal of the N−1th-stage GOA, a source of the sixth transistor electrically connects the second node, a drain of the sixth transistor electrically connects the second negative supply, a gate of the seventh transistor electrically connects the second clock signal, a source of the seventh transistor electrically connects the first clock signal, a drain of the seventh transistor electrically connects the second node, a gate of the eighth transistor electrically connects the second node, a source of the eighth transistor electrically connects the output terminal, a drain of the eighth transistor electrically connects a first negative supply, a gate of the ninth transistor electrically connects the second node, a source of the ninth transistor electrically connects the first node, a drain of the ninth transistor electrically connects the second negative supply, a gate of the tenth transistor electrically connects the second node, a source of the tenth transistor electrically connects the driving signal terminal, a drain of the tenth transistor electrically connects a third negative supply, wherein the fifth transistor and the sixth transistor are used for pulling down the electrical potential of the second node when the driving signal terminal is in a high electrical potential; wherein the second pull-down holding circuit having a eleventh transistor and a twelfth transistor; wherein a gate of the eleventh transistor electrically connects a driving signal terminal of the N+2th-stage GOA, a source of the eleventh transistor electrically connects the first node, a drain of the eleventh transistor electrically connects the second negative supply, a gate of the twelfth transistor electrically connects the driving signal terminal of the N+2′-stage GOA, a source of the twelfth transistor electrically connects the output terminal, a drain of the twelfth transistor electrically connects the first negative supply; a pull-down part having a thirteenth transistor and a fifteenth transistor, wherein a gate of the thirteenth transistor electrically connects a driving signal terminal of the N+1th-stage GOA, a source of the thirteenth transistor electrically connects the driving signal terminal, a drain of the thirteenth transistor electrically connects the third negative supply, a gate of the fifteenth transistor electrically connects the driving signal terminal of the N+1th-stage GOA, a source of the fifteenth transistor electrically connects the first node, a drain of the fifteenth transistor electrically connects the second negative supply, wherein the thirteenth transistor is used for pulling down the electrical potential of the driving signal terminal to prevent the electrical leakages of the fifth transistor and the sixth transistor when the gate driver circuit is not working, wherein the fifteenth transistor is used for pulling down the electrical potential of the first node rapidly when the output terminal finishes outputting before next stage begins; a boost part having a capacitor, wherein the capacitor electrically connects the first node and the output terminal, wherein the boost part is used for pulling up the electrical potential of the first node again to make sure the output terminal of the pull-up part outputs normally; and channels of the TFT switches of the gate driver circuit basing on the IGZO process are oxide semiconductor channels.