MECHANISM TO PRECLUDE LOAD REPLAYS DEPENDENT ON FUSE ARRAY ACCESS IN AN OUT-OF-ORDER PROCESSOR

摘要

An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include a fuse array that stores configuration data.

主权项

1. An apparatus for reducing replays in an out-of-order processor, the apparatus comprising:
a first reservation station, configured to dispatch a first load micro instruction, and configured to detect and indicate on a hold bus if said first load micro instruction is a specified load micro instruction directed to one of a plurality of non-core resources; a second reservation station, coupled to said hold bus, configured to dispatch one or more younger micro instructions therein that depend on said first load micro instruction for execution after a first number of clock cycles following dispatch of said first load micro instruction, and if it is indicated on said hold bus that said first load micro instruction is said specified load micro instruction, said second reservation station is configured to stall dispatch of said one or more younger micro instructions until said first load micro instruction has retrieved said operand; and said plurality of non-core resources, comprising:
a fuse array, configured to store configuration data corresponding to the out-of-order processor.