Semiconductor memory device having circuit array structure for fast operation

摘要

In a semiconductor memory device including at least four memory cell array blocks (200) constituted by arraying memory cells and row and column decoders (30,40) for respectively controlling word lines and bit lines being disposed inside each of the memory cell array blocks (200), the semiconductor memory device includes an input/output lines (7) for inputting/outputting data of the memory cell array block, input/output means (8), connected to the input/output lines (7), for controlling and driving input/output of the data, first data lines (13) for transmitting the data, being disposed between the input/output means (8) of one memory cell array block (200) and the input/output means (8) of another memory cell array block (200) arranged in a vertical direction with respect to the one memory cell array block, second data lines (15) for transmitting the data by connecting the first data lines (13) of at least two memory cell array blocks (200) disposed in a horizontal direction, data buffer means (9), connected to the second data lines (15), for sensing and amplifying the data, and a data input/output pads (10), connected to the data buffer means (9), for inputting/outputting the data to and from an external lead frame. Therefore, the present invention has an effect in that a relatively small layout area and low power consumption during circuit operation can be achieved. <IMAGE>