| 摘要 |
<p>A clock frequency limiting circuit is disclosed. The clock frequency limiting circuit allows a semiconductor device to be fabricated, packaged and tested before the maximum clock frequency is set. The maximum clock frequency is set by burning a bank of on-chip fuses (250). The clock frequency limiting circuit counts clock cycles (120) of an applied clock signal for a predetermined amount of time. A comparator (130) compares the maximum clock frequency in the fuse bank (250) and the counted clock cycles (120). A violation 'kill' signal (155) is asserted if the counted clock cycles (120) exceed the set maximum clock frequency.</p> |
