发明名称 |
Discrete three-dimensional memory |
摘要 |
The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least an off-die peripheral-circuit component of the 3D-M arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures. |
申请公布号 |
US9396764(B2) |
申请公布日期 |
2016.07.19 |
申请号 |
US201514884755 |
申请日期 |
2015.10.15 |
申请人 |
HangZhou HaiCun Information Technology Co., Ltd. |
发明人 |
Zhang Guobiao |
分类号 |
G11C5/02;H01L25/065;G11C5/14;G11C7/00;G11C8/14;G11C5/04;G11C13/00;H01L23/00;H01L25/10;G11C29/04 |
主分类号 |
G11C5/02 |
代理机构 |
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代理人 |
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主权项 |
1. A discrete three-dimensional memory (3D-M), comprising:
a 3D-array die comprising at least a 3D-M array, wherein said 3D-M array comprises a plurality of vertically stacked memory levels; a peripheral-circuit die comprising at least an off-die peripheral-circuit component of said 3D-M array, wherein said off-die peripheral-circuit component is absent from said 3D-array die; means for coupling said 3D-array die and said peripheral-circuit die; wherein the number of address-line levels in said 3D-array die is at least twice as much as the number of interconnect levels in said peripheral-circuit die; and, said 3D-array die and said peripheral-circuit die are separate dice. |
地址 |
HangZhou, ZheJiang CN |