METHOD FOR WAFER LEVEL RELIABILITY

摘要

A method for ensuring wafer level reliability is provided. The method involves: forming a gate oxide layer having a thickness of less than 50 Å on a semiconductor substrate; forming a PMOS element having a channel length of less than 0.13 μm on the semiconductor substrate; and assessing hot carrier injection (HCl) for the PMOS element.

主权项

1. A method for ensuring wafer level reliability, comprising:
forming a trench on a semiconductor substrate; forming a sidewall oxide layer and a liner nitride layer on the trench; filling an insulating material on the liner nitride layer; forming a PMOS element on the semiconductor substrate; and assessing hot electron induced punch through (HEIP) for the PMOS element.