| 摘要 |
PURPOSE: A semiconductor memory unit with improved power line alignment is provided to improve reliability of the unit by reducing chip area and supplying sufficient power to the chip. CONSTITUTION: Memory cell array region consisting of memory cell array blocks(303A,303B,303C,303D) is extended to a first direction of a chip. Bit lines(BL0,BL1,BLn-1,BLn) parallel along the row are aligned as a first metal layer with an insulation layer interposing on top of each block of the extended memory cell array blocks(303A,303B,303C,303D). Excluding top of bit lines(BL0 and BL1 for 303A) with memory cell array extended among the bit lines(BL0,BL1,BLn-1,BLn), a second metal layer is interposed on top of the first metal layer as another insulation layer.
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