Low read current architecture for memory

摘要

A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

主权项

1. An integrated circuit, comprising:
a plurality of bit lines; a plurality of word lines; a plurality of re-writeable non-volatile resistive state memory elements (ME's), each ME is positioned at an intersection of one of the word lines with one of the bit lines, each ME comprising a first terminal electrically coupled with its respective word line and a second terminal electrically coupled with its respective bit line, and each ME is to store at least one-bit of non-volatile data; pre-charge circuitry to apply a first voltage to the plurality of bit lines; word line circuitry to apply a second voltage to a selected word line of the plurality of word lines and to apply the first voltage to an unselected remainder of the plurality of word lines; a reference cell comprising a first terminal electrically coupled with a reference bit line and a second terminal electrically coupled with the selected word line; and multi-sensing read circuitry coupled to the plurality of bit lines and the reference bit line, the multi-sensing read circuitry to:
simultaneously sense a voltage change during a sensing window of more than one bit line of the plurality of bit lines using a respective plurality of sense amplifiers responsive to applying the second voltage to the selected word line and applying the first voltage to the unselected word lines; andoutput read data indicative of the current on each of the more than one bit lines, respectively, responsive to simultaneously sensing the more than one bit line of the plurality of bit lines using the plurality of sense amplifiers.