发明名称 System and method for conditional task switching during ordering scope transitions
摘要 A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The hardware module stores a first ordering scope identifier at a first storage location of the ordering scope manager. The first ordering scope identifier indicates a first ordering scope that a first task is operating in. The ordering scope manager increments the first ordering scope identifier to create a new ordering scope identifier. In response to determining that the processor core is authorized to transition the first task from the first ordering scope to a second ordering scope associated with the new ordering scope identifier, the ordering scope manager provides hint information to the processor core. The processor core transitions from the first ordering scope to the second ordering scope without completing a task switch in response to the hint information.
申请公布号 US9372724(B2) 申请公布日期 2016.06.21
申请号 US201414231789 申请日期 2014.04.01
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 Xu Zheng;Jokinen Tommi M.;Moyer William C.
分类号 G06F9/48 主分类号 G06F9/48
代理机构 代理人
主权项 1. A method comprising: storing a first ordering scope identifier at a first storage location of an ordering scope manager, wherein the first ordering scope identifier indicates a first ordering scope that a first task is operating in, the first task being executed by a processor core; incrementing the first ordering scope identifier to create a new ordering scope identifier; in response to determining that that the first task is authorized to transition from the first ordering scope to a second ordering scope associated with the new ordering scope identifier, providing hint information from the ordering scope manager to the processor core; setting a first storage location of the processor core to a first state in response to the hint information; and in response the first storage location of the processor core being in the first state, transitioning the processor core to the second ordering scope without completing a task switch, otherwise requesting, by the processor core, permission to exit the current ordering scope during the task switch in response to the first storage location being in a second state.
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