| 摘要 |
<p>PROBLEM TO BE SOLVED: To obtain a high-speed floating gate charge detecting CCD delay unit by driving clamp-and-hold circuits with a plurality of clock signals, each clamp-and-hold circuit serving to clamp a voltage equal to or greater than a predetermined voltage from voltages of detecting electrodes and to hold the clamped voltage for a predetermined time interval. SOLUTION: Delay taps are formed of electrode portions G1 to G4 and electrode portions G5 to G8 on a CCD delay line, respectively, with the portions G1 to G4 be connected in a reverse phase with the portions G5 to G8. Each of the portions G2 and G6 doubles as a drive electrode and a detecting gate. The gates G2 and G6 are connected to clamp-and-hold circuit CH through capacitors C3 and C4, respectively. Each circuit CH is driven by a clock of four phasesϕ1 toϕ4 of the corresponding ones of the portions G1 to G8, thereby clamping a voltage equal to or greater than a predetermined voltage from a voltage of the corresponding one of the gates G2 and G6 and holding the clamped voltage for a predetermined time interval. As a result, a high-speed floating gate charge detecting CCD delay unit can be obtained.</p> |
