发明名称 |
Flash memory device supporting cache read operation |
摘要 |
A flash memory device comprises a non-volatile memory core operatively connected to first and second buffer memories through a page buffer. The device further comprises a first register adapted to receive command and address information from a host system, a copy circuit adapted to copy the command and address information from the first register to a second register within a control logic circuit. The device alternately transfers information to the first and second buffer memories during a cache read operation comprising a plurality of data read operations.
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申请公布号 |
US2006224820(A1) |
申请公布日期 |
2006.10.05 |
申请号 |
US20050311589 |
申请日期 |
2005.12.16 |
申请人 |
CHO HYUN-DUK;CHOI YOUNG-JOON;KIM TAE-GYUN |
发明人 |
CHO HYUN-DUK;CHOI YOUNG-JOON;KIM TAE-GYUN |
分类号 |
G06F12/00;G06F13/28 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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