| 摘要 |
<p>PURPOSE:To allow or inhibit the output of a signal indicating the start of a bus cycle by allowing a bus cycle start signal generator to input an internal timing clock signal and a trigger signal and output a bus cycle start delay signal corresponding to an external timing switching input signal corresponding to an external timing switching input signal. CONSTITUTION:The bus control structure of a microcomputer(MC) to be used in a development supporting device includes a timing signal generator 102 for inputting a cycle request signal and a timing clock signal and supplying a trigger signal to a bus cycle start signal generator 113. The generator 113 inputs an internal timing clock signal and the trigger signal and outputs a bus cycle start delay signal correspondingly to an external timing switching input signal. Namely, the output timing of a signal indicating the start of the bus cycle can be delayed from the output timing of an address signal. Consequently, the permission or inhibition of the output of the signal indicating the start of the bus cycle to the outside of the development supporting device can be controlled by utilizing the delay time.</p> |
