发明名称 |
Voltage level shifter module |
摘要 |
A voltage level shifter module comprising at least one input arranged to receive an input signal, and at least one cascode transistor arranged to receive at a gate thereof at least one reference voltage signal. The voltage level shifter module further comprises at least one reference voltage control component arranged to detect logical state transitions within the input signal from at least a first logical state to a second logical state, and cause the reference voltage signal applied to the gate of the at least one cascode transistor to be pulled down to a reduced voltage upon detection of a logical state transition within the input signal from at least a first logical state to a second logical state. |
申请公布号 |
US9484922(B2) |
申请公布日期 |
2016.11.01 |
申请号 |
US201414516656 |
申请日期 |
2014.10.17 |
申请人 |
Freescale Semiconductor, Inc. |
发明人 |
Malkov Andrey Evgenevich |
分类号 |
H03K19/018;H03K19/0185;H03K3/356;H03K5/06;H03K5/15;H03K5/1534 |
主分类号 |
H03K19/018 |
代理机构 |
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代理人 |
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主权项 |
1. A voltage level shifter module comprising:
at least one input arranged to receive an input signal; and at least one cascode transistor arranged to receive at a gate thereof at least one reference voltage signal; wherein the voltage level shifter module further comprises at least one reference voltage control component arranged to: detect logical state transitions within the input signal from at least a first logical state to a second logical state; cause the reference voltage signal applied to the gate of the cascode transistor to be pulled down to a reduced voltage upon detection of a logical state transition within the input signal from the first logical state to the second logical state; and wherein the reference voltage control component includes at least one of,
an AND gate arranged to receive the input signal and an inverted form of the input signal and to output a first logic pulse upon the logical state transition; ora NAND gate arranged to receive the input signal and the inverted form of the input signal and to output a second logic pulse upon the logical state transition. |
地址 |
Eindhoven NL |