发明名称 |
MEMORY DEVICE HAVING VARIOUS DELAY |
摘要 |
A memory device having variable delay is provided to improve speed margin of the memory device, by enabling to set small delay of a write enable signal and a read enable signal in a normal mode. A delay part(250) delays a pulse signal to generate a write enable signal and a read enable signal. A delay selection part(260) adjusts the pulse signal not to pass through the delay part in a normal mode, in order for the pulse signal to pass through the delay part in a test mode. The test mode is a burn-in test mode applying a high voltage to a memory device.
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申请公布号 |
KR100815179(B1) |
申请公布日期 |
2008.03.19 |
申请号 |
KR20060134360 |
申请日期 |
2006.12.27 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
JANG, JI EUN;KIM, KYUNG WHAN |
分类号 |
G11C8/00;G11C7/22;G11C29/06 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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