发明名称 MEMORY CONTROLLER
摘要 PROBLEM TO BE SOLVED: To reduce circuit scale, to flexibly cope with a change of application, etc., and to enhance reusability regarding a memory controller by preferably being used for the real time processing application having many kinds of memory access factors such as MPEG CODEC and a digital broadcast receiver, etc. SOLUTION: The memory controller is provided with a system interface circuit 9 to mediate a plurality of access requests (a) to (n) from an accessing origin of an SDRAM 7 and to extract a block to access the SDRAM 7. An address engine 10 and a command sequence control circuit 11 common to the plurality of access factors (a) to (n) are installed on the rear stage of the system interface circuit 9.
申请公布号 JP2002328837(A) 申请公布日期 2002.11.15
申请号 JP20010131116 申请日期 2001.04.27
申请人 FUJITSU LTD 发明人 KYO REI;WATABE YASUHIRO
分类号 G06F12/06;G06F12/00;(IPC1-7):G06F12/06 主分类号 G06F12/06
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