摘要 |
A calculating unit including a number of bit slices which is less than the number of positions of the operand to be processed. Each bit slice has a logic element and a communication bus between the logic element and the plurality of register cells. The register cells are connected in parallel with respect to the slice-internal communication bus and are controlled by a controller so that only one register cell of the plurality of register cells is coupled to the communication bus at a time.
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