Decision feedback equalization

摘要

A signal sampling system that includes N samplers is disclosed. Each sampler includes a data input having a decision logic level threshold, a plurality of offset control inputs, a plurality of offset magnitude inputs, an un-buffered output, and a buffered output. Each sampler further includes circuitry coupled between the inputs and outputs that is configured to cause a time delay from an input signal transition to an output signal transition such that, after an offset control input transitions from a first voltage to a second voltage, the decision logic level threshold changes in a time substantially less than one gate delay, and after the sample clock transitions from a first logic state to a second logic state, the un-buffered output transitions within a time substantially equal to one gate delay and the buffered output transitions within a time substantially equal to two gate delays.

主权项

1. A signal sampling system comprising N latching samplers, wherein
N is an integer equal to or greater than four; each sampler of the N latching samplers includes a sample clock input to couple to a sample clock, and the sample clocks of the N latching samplers are spaced in phase through 360 degrees; each sampler of the N latching samplers further includes a data input having a decision logic level threshold, a plurality of offset control inputs, a plurality of offset magnitude inputs, an un-buffered output, and a buffered output; and each sampler of the N latching samplers further includes circuitry coupled between the inputs and outputs that causes a time delay from an input signal transition to an output signal transition wherein, after an offset control input changes from a first voltage to a second voltage, the decision logic level threshold changes in a time less than one gate delay, and after the sample clock transitions from a first logic state to a second logic state, the un-buffered output transitions within a time substantially equal to one gate delay and the buffered output transitions within a time substantially equal to two gate delays.