Flash memory apparatus and data erasing method thereof

摘要

A flash memory apparatus and data erasing method thereof. The data erasing method includes: setting a plurality of incremental erasing voltages sequentially, and operating a plurality of data erasing operations on memory cells according to the erasing voltages; recording a recoded erasing voltage corresponding to the last data erasing operation; setting a plurality of incremental reading voltage sequentially, operating a plurality of data reading operations on the memory cells, and recording a final reading voltage corresponding to the last reading operation; setting a final erasing voltage for operating a final erasing operation on the memory cells, wherein a voltage level of the final erasing voltage equals to a sum of voltage levels of an erasing verification voltage, the final reading voltage and the recorded erasing voltage.

主权项

1. A data erasing method for flash memory, comprising:
setting a plurality of erasing voltages increased by an incrementing level sequentially and respectively performing a plurality of data erasing operations on the memory cells of a flash memory according to the erasing voltages; performing a normal reading operation on the memory cells after each time of the data erasing operations, and determining whether or not a next data erasing operation is needed according reading results of the normal reading operation, and recording a last one of the erasing voltages of a last time of the data erasing operations as a recorded erasing voltage; setting a plurality of reading voltages increasing with an incremental value sequentially after an end of the data erasing operations, and performing a plurality of reading operations on the memory cells according to the reading voltages, wherein reading results of the reading operations are used to determine whether or not a next reading operation is needed and recording a final reading voltage level for a last time of the reading operations; and setting a final erasing voltage to perform a final erasing operation on the memory cells, wherein a voltage level of the final erasing voltage is equal to a sum of a voltage level of an erasing verification voltage, a voltage level of the final reading voltage, and a voltage level of the recorded erasing voltage.