| 摘要 |
A semiconductor memory device including a memory core block, a logic circuit and a direct access circuit which control the memory core block, and a delay pulse generation circuit. The logic circuit generates first and second internal clock signals responsive to first and second external clock signals, and operates the memory core block at high speed during a normal operation. The direct access circuit generates first and second internal clock signals responsive to first and second external clock signals, to test the memory core block during a direct access operation. The delay pulse generation circuit generates a pulse signal corresponding to the delay difference between the first and second internal clock signals generated by the direct access circuit. The delay difference is used by a tester to compensate for actual delay of the internal clock signals when the memory core block is tested during the direct access operation.
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