发明名称 Wafer Level Integrated Circuit Contactor and Method of Construction
摘要 A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). The elastomer is precompressed from its natural rest state between a top (22) plate and a bottom (70). Pre compression improves the resilient response of the pins. The pin crowns (40) are maintained relatively coplanar by the engagement of at least one flange (44a-b) against an up-stop surface 90 of plate 20, thereby insuring coplanarity of the crowns. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.
申请公布号 US2016161528(A1) 申请公布日期 2016.06.09
申请号 US201615043898 申请日期 2016.02.15
申请人 Johnstech International Corporation 发明人 Edwards Jathan;Marks Charles;Halvorson Brian
分类号 G01R1/067;G01R31/26;G01R1/073 主分类号 G01R1/067
代理机构 代理人
主权项 1. A test contact pin assembly for temporary contact with a test pad on a wafer level integrated circuit device under test (DUT) comprising: a. at least one slideable upper terminal pin, further having, a top extension for contacting the DUT, portion, at least one lateral cross member flange and a contact surface; said upper pin being slideable between an out of test position and an in-test position; b. at least one lower terminal pin having a foot and a like contact surface; c. said upper and lower pins being held in contact by bias forces which maintain their respective contacts surfaces together but in a slideable relationship to each other; d. an elastomeric material of predetermined height when in an uncompressed state, said material surrounding the pins to create said bias force; e. a substantially rigid top pin guide surface located atop said elastomeric material, including a pair of spaced part parallel walls defining a guide channel for said flange, an upper wall between said parallel walls defining an up-stop surface for said pin and an aperture in said up-stop surface for receiving an extended portion of said upper pin which protrudes beyond said guide surface to make contact with said DUT, said channel being sized to be large enough to receive said flange with minimum frictional contact the parallel walls; said up-stop surface providing an upward stop limit for the upper pin by virtue of its contact with the flange, f. said guide channel having a depth sufficient to contain said flange against rotation between pin travel distance occurring from said out of test position and said in test position, so that said upper and lower pin contacts surfaces are maximally in contact with each other throughout the pin travel distance.
地址 Minneapolis MN US