发明名称 |
Method and apparatus for resetting a memory upon power recovery |
摘要 |
A method and apparatus for resetting memory state when power is applied to the system. The memory has memory elements, a refresh clock and a refresh counter for counting refresh cycles and providing refresh signals to the memory elements, the memory elements and refresh means being connected from the power system and from a battery back-up means. A state detection means is connected from the refresh counter for detecting a change in state of the refresh counter to a state equivalent to the reset state of the refresh counter and asserting a state change signal. A means responsive to the state change signal and to the occurrence of the reset signal provides a memory controller reset signal, so that the memory controller reset signal occurs in synchronization with the change of state of the refresh counter to a state equivalent to the refresh counter reset state. The memory reset further includes a time-out counter means responsive to the assertion of the reset signal and to the refresh clock for counting refresh cycles in synchronization with the refresh counter. A time-out detection means is responsive to the time out counter means for providing a time out signal when the time-out counter has counted a refresh period plus one clock cycle and to the state change signal for providing the memory controller reset signal when the time-out counter has counted a refresh cycle plus one clock period and the state change signal has not been asserted. |
申请公布号 |
US5204964(A) |
申请公布日期 |
1993.04.20 |
申请号 |
US19900593917 |
申请日期 |
1990.10.05 |
申请人 |
BULL HN INFORMATION SYSTEMS INC. |
发明人 |
BOWDEN, III, RAYMOND D.;PENCE, MICHELLE A.;BARLOW, GEORGE J.;SANFACON, MARC E.;SOMERS, JEFFREY S. |
分类号 |
G06F11/14;G06F11/20;G11C7/20;G11C11/406 |
主分类号 |
G06F11/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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