发明名称 Method and apparatus for pre-computing placement costs
摘要 Some embodiments of the invention provide a method that pre-computes costs of placing circuit modules in regions of circuit layouts. The method defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a placement operation. For each set of potential sub-regions, the method identifies a connection graph that traverses the set of potential sub-regions. Some of the connection graphs have edges that are at least partially diagonal. The method then identifies an attribute of each identified connection graph. For each set of potential sub-regions, the method then stores the identified attribute of the connection graph that is identified for the set.
申请公布号 US6904580(B2) 申请公布日期 2005.06.07
申请号 US20020079061 申请日期 2002.02.20
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 TEIG STEVEN;GANLEY JOSEPH L.
分类号 G06F17/50;G11B7/085;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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