发明名称 |
Field programmable gate array core cell with efficient logic packing |
摘要 |
A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.
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申请公布号 |
US2005040849(A1) |
申请公布日期 |
2005.02.24 |
申请号 |
US20040951309 |
申请日期 |
2004.09.27 |
申请人 |
LEOPARD LOGIC, INC. |
发明人 |
PUGH DANIEL J.;FOX ANDREW W.;WONG DALE |
分类号 |
G06F17/50;(IPC1-7):H03K19/177 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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