发明名称 Integrated inductor and magnetic random access memory device
摘要 Devices and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first upper dielectric layer is provided over the substrate. The first upper dielectric layer comprises a first upper interconnect level with a plurality of metal lines. A dielectric layer is formed over the first upper dielectric layer. The dielectric layer includes a second upper interconnect level with a plurality of metal lines. A magnetic random access memory (MRAM) cell is formed between the first and second upper interconnect levels in the first region. An inductor is formed in the second region. The inductor includes a lower inductor level formed from metal lines in the first upper interconnect level and an upper inductor level formed from metal lines in the second upper interconnect level. The metal lines in the lower inductor level and upper inductor level are coupled by via contacts to form loops of the inductor.
申请公布号 US9397139(B1) 申请公布日期 2016.07.19
申请号 US201514862174 申请日期 2015.09.23
申请人 GLOBALFOUNDRIES SINGAPORE PTE. LTD. 发明人 Tan Juan Boon;Jiang Yi;Yi Wanbing;Shum Danny Pak-Chum
分类号 H01L27/22;H01F27/28;H01L43/02;H01L43/12;H01L49/02 主分类号 H01L27/22
代理机构 Horizon IP Pte. Ltd. 代理人 Horizon IP Pte. Ltd.
主权项 1. A method of forming a device comprising: providing a substrate defined with at least first and second regions; providing a first upper dielectric layer over the substrate, wherein the first upper dielectric layer comprises a first upper interconnect level with a plurality of metal lines in the first and second regions; providing a dielectric layer over the first upper dielectric layer, wherein the dielectric layer comprises a second upper interconnect level with a plurality of metal lines in the first and second regions; forming a magnetic random access memory (MRAM) cell, wherein the MRAM cell is disposed between the first and second upper interconnect levels in the first region; and forming an inductor in the second region, wherein the inductor comprises a lower inductor level formed from the metal lines in the first upper interconnect level and an upper inductor level formed from the metal lines in the second upper interconnect level, wherein the metal lines in the lower inductor level and upper inductor level are coupled by via contacts to form loops of the inductor.
地址 Singapore SG