| 摘要 |
A framing pattern detector comprises a multi-stage input store, an intermediate logic operator, and a decoder. As the serial bit stream is clocked through the input store, the intermediate logic operator subjects sequentially spaced apart bits to a prescribed logic function, and transforms these bits into a transformed bit pattern having a length less than that of the framing pattern. The decoder compares the transformed bit pattern with cyclically rotated versions of a prescribed multi-bit framing pattern template. In response to a match between the transformed pattern with any of the cyclically rotated versions of the template, the decoder identifies the framing pattern. If the decoder fails to detect a match, the clocking of the serial bit stream is adjusted until the decoder identifies the framing pattern.
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