| 摘要 |
PROBLEM TO BE SOLVED: To realize a high speed memory operation by a method wherein a clock for an FF which outputs a memory control signal is supplied from a PLL which includes an independent circuit which is equivalent to a control signal output circuit and delays other than the delay caused by a DRAM are seemingly eliminated. SOLUTION: Control signals which are supplied from the output Q of an FF 50 drive a DRAM 10 and a plurality of other DRAM's through control lines. When a predetermined lapse of time passes after the control signal is inputted to the DRAM 10, the DRAM 10 outputs data. The outputted data are sampled by an FF 60. An FF 70 has the same characteristics as the FF 50 and a clock signal identical to a clock signal for the FF 50 is inputted from a PLL 40. The FF 70 drives an artificial load 20 which is equivalent to control lines and a plurality of DRAM's to produce a delay equal to the delay caused by the FF 50. The PLL 40 adjusts an output clock so as to make the phase of the system clockϕof an R-terminal identical to the phase of the input signal of the load 20 of a C-terminal. With this constitution, the delays other than the delay caused by the DRAM are seemingly made to be zero and the high speed memory operation can be realized.
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