发明名称 Clocked state devices including master-slave terminal transmission gates and methods of operating same
摘要 A clocked state circuit can include a transmission gate configured to clock an output of a master terminal to an input of a slave terminal responsive to a clock signal or a delayed clock signal coupled to the transmission gate.
申请公布号 US7301381(B2) 申请公布日期 2007.11.27
申请号 US20050194272 申请日期 2005.08.01
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 RHEE YOUNG-CHUL;CHO SUNG-WE
分类号 H03K3/289 主分类号 H03K3/289
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