Method and apparatus for performing integrated circuit layout verification

摘要

A method of performing layout verification for an integrated circuit (IC) layout is described. The method comprises receiving layout information for the IC layout, identifying at least one IC component within the IC layout, extracting localized layout information for the at least one IC component from the received layout information, defining the localized layout information for the at least one IC component within at least one component instance parameter therefor, and performing at least one layout verification check for the at least one component based at least partly on the at least one component instance parameter.

主权项

1. A computer system executed method of performing layout verification for an integrated circuit (IC) layout; the method comprising:
receiving layout information for the IC layout; identifying at least one IC component within the IC layout; extracting localised layout information for the at least one IC component from the received layout information, wherein the localised layout information comprises an indication that the at least one IC component is located within a designer marked area; defining the localised layout information for the at least one IC component within at least one IC component instance parameter therefor; and performing at least one layout verification check for the at least one IC component within the designer marked area based at least partly on the at least one IC component instance parameter to verify a mask set for the IC that would be manufactured in a semiconductor manufacturing process based on the verified mask set, wherein the performing the at least one layout verification check utilizes at least one layout verification check value that is modified by increasing the at least one layout verification check value by a percentage value.