Shift register unit, gate driving apparatus and display device

摘要

Provided is a shift register unit, a gate driving apparatus and a display device capable of increasing a lifespan of a shift register. The shift register unit according to the present disclosure includes: a first thin film field effect transistor, a drain thereof connected with a first signal terminal, a source thereof connected with the outputting node at the present stage, a gate thereof connected with a first node; a second thin film field effect transistor, a drain thereof connected with the first signal terminal, a source thereof connected with the pulling-up node, and a gate thereof connected with the first node; a third thin film field effect transistor, a drain thereof connected with a second signal terminal, a source thereof connected with the outputting node at the present stage, and a gate thereof connected with a second node; a fourth thin film field effect transistor, a drain thereof connected with the second signal terminal, a source thereof connected with the pulling-up node, and a gate thereof connected with the second node; and a node voltage control module, configured to control the first node and the second node to be in a high potential state alternatively when the shift register unit is in a pulling-down phase. The present disclosure increases the lifespan of the shift register.

主权项

1. A shift register unit comprising a capacitor, wherein one terminal of the capacitor is connected with an outputting node at a present stage, and the other terminal of the capacitor is connected with a pulling-up node, and the shift register unit further comprises:
a first thin film field effect transistor, a drain thereof connected with a first signal terminal, a source thereof connected with the outputting node at the present stage, a gate thereof connected with a first node; wherein the first signal terminal is configured to output a low potential signal when the first thin film field effect transistor is turned on; a second thin film field effect transistor, a drain thereof connected with the first signal terminal, a source thereof connected with the pulling-up node, and a gate thereof connected with the first node; wherein the first signal terminal is configured to output the low potential signal when the second thin film field effect transistor is turned on; a third thin film field effect transistor, a drain thereof connected with a second signal terminal, a source thereof connected with the outputting node at the present stage, and a gate thereof connected with a second node; wherein the second signal terminal is configured to output the low potential signal when the third thin film field effect transistor is turned on; a fourth thin film field effect transistor, a drain thereof connected with the second signal terminal, a source thereof connected with the pulling-up node, and a gate thereof connected with the second node; wherein the second signal terminal is configured to output the low potential signal when the fourth thin film field effect transistor is turned on; and a node voltage control module, configured to control the first node and the second node to be in a high potential state alternatively when the shift register unit is in a pulling-down phase; and a first resetting unit configured to output the low potential signal to the pulling-up node and the outputting node at the present stage under a control of a reset signal, wherein the first resetting unit comprises: a first resetting thin film field effect transistor, a source thereof configured to receive a first clock control signal, a drain thereof connected with the first node, and a gate thereof configured to receive the reset signal; and a second resetting thin film field effect transistor, a source thereof configured to receive a second clock control signal, a drain thereof connected with the second node, and a gate thereof configured to receive the reset signal; wherein the node voltage control module comprises a first node voltage control sub-module, and the first node voltage control sub-module comprises: a fifth thin film field effect transistor, a source and a gate thereof configured to receive the first clock control signal, and a drain thereof connected with the first node; and a sixth thin film field effect transistor, a drain thereof configured to receive the low potential signal, a source thereof connected with the second node, and a gate thereof configured to receive the first clock control signal.