SEMICONDUCTOR DEVICE, POWER CONTROL METHOD, AND STORAGE MEDIUM

摘要

According to an embodiment, a semiconductor device can be in an operating state and a standby state with a choice of a plurality of standby state levels and has a CPU, an interrupt control circuit, and a hardware control circuit. The CPU makes a comparison of a first return time period corresponding to a first standby state level that is a shallowest one selected from among allowable standby state levels set for one or more tasks executed immediately before transition to the standby state with a second return time period selected from among allowable return time periods set for the one or more tasks executed, changes a standby state level of the standby state if the first return time period is judged to be longer than the second return time period as a result of the comparison, and controls the hardware control circuit.

主权项

1. A semiconductor device capable of being in an operating state and a standby state with a choice of a plurality of standby state levels, comprising:
a CPU capable of executing a plurality of tasks; an interrupt control circuit configured to generate an interrupt signal for transition from the standby state to the operating state; and a power control circuit configured to control operation of each of a plurality of hardware circuits and control power consumed by the plurality of hardware circuits, under control of the CPU, wherein the CPU makes a comparison of a first return time period corresponding to a first standby state level that is a shallowest one selected from among allowable standby state levels set for one or more tasks executed immediately before transition to the standby state with a shortest first allowable return time period selected from among allowable return time periods set for the one or more tasks executed, and sets a standby state level of the standby state to the first standby state level if the first return time period is judged to be not more than the first allowable return time period, changes the standby state level of the standby state to a second standby state level having a return time period shorter than the first return time period if the first return time period is judged to be longer than the first allowable return time period, and controls the power control circuit.