Configurable peripheral componenent interconnect express (PCIe) controller

摘要

In an system on a chip, multiple PCIe controllers may be present in which each PCIe controller may be configured to route input data to either itself or to another PCIe controller based on a priority level of the input data. Similarly, each PCIe controller may be configured to route output data by way of its own PCIe link or that of another PCIe controller based on a scheduling order which may be based on a priority level of the buffer in which the output data is stored. In this manner, multiple PCIe controllers which, in a first mode, are capable of operating independently from each other can be configured, in a second mode, to provide multiple channels for a single PCIe link, in which each channel may correspond to a different priority level.

主权项

1. A peripheral component interconnect express (PCIe) controller comprising:
an ingress buffer; an egress buffer; a first ingress transaction-level selection logic configured to select a first or a second data input signal as an ingress data signal, wherein:
the second data input signal originates from a second PCIe controller; andthe first ingress transaction-level selection logic is enabled by a configuration signal; a second ingress transaction-level selection logic communicatively coupled to the first ingress transaction-level selection logic, the second ingress transaction-level selection logic configured to:
receive the ingress data signal from the first ingress transaction-level selection logic; andcommunicate the ingress data signal to the ingress buffer or a second packet decoder based at least on an ingress transaction steering signal, wherein the ingress transaction steering signal is configured to indicate a priority level associated with the ingress data signal, the priority level having been decoded at a transaction level by a first packet decoder; and an egress transaction-level selection logic configured to select a first or a second data output signal to an egress data signal, wherein:
the second data output signal originates from the second PCIe controller; andthe egress transaction-level selection logic is enabled by an egress transaction steering signal, the egress transaction steering signal configured to indicate a scheduling order associated with the PCIe controller and the second PCIe controller.