发明名称 Circuits and methods for fault testing
摘要 An integrated circuit sensor includes circuitry and methods for generating a high speed delay fault test clock signal. A trimmable oscillator generates a master clock signal for use by an output protocol processor to provide the sensor output signal. A fault test clock signal generator is responsive to the master clock signal and to a test trigger signal for generating the test clock signal having a launch pulse and a capture pulse, each having edges substantially coincident with like edges of pulses of the master clock signal and a spacing between launch and capture pulses established by the trimmable master clock signal.
申请公布号 US9513337(B2) 申请公布日期 2016.12.06
申请号 US201113290293 申请日期 2011.11.07
申请人 Allegro Microsystems, LLC 发明人 Forrest Glenn A.;Cook Aaron;Briere Dana;Fernandez Devon;Nakayama Naota
分类号 G01R31/3185 主分类号 G01R31/3185
代理机构 Daly, Crowley, Mofford & Durkee, LLP 代理人 Daly, Crowley, Mofford & Durkee, LLP
主权项 1. An integrated circuit sensor comprising: an oscillator for generating a master clock signal that is used by the integrated circuit sensor both when the integrated circuit sensor is functioning in a test mode and when the integrated circuit sensor is functioning in a normal operational mode, wherein, when the integrated circuit sensor is functioning in a test mode, a frequency of the master clock signal is based at least in part on an externally generated programming signal provided to the integrated circuit sensor; a fault test clock signal generator responsive to the master clock signal and to a test trigger signal, the fault test clock signal generator configured to generate, during test of the integrated circuit sensor when the integrated circuit sensor is functioning in its test mode, a test clock signal derived at least in part from the master clock signal, wherein the test clock signal comprises a launch pulse and a capture pulse used during at least a portion of delay fault testing of the integrated circuit sensor, the launch and capture pulses having a controllable time spacing between an edge of the launch pulse and an edge of the capture pulse, wherein different values of the controllable time spacing are usable for different fault tests, and wherein the controllable time spacing is controlled based at least in part on information conveyed via the externally generated programming signal; and an output processor responsive to the master clock signal and to information provided by the integrated circuit sensor relating to a ferromagnetic article disposed in proximity to the integrated circuit sensor when the integrated circuit sensor is functioning in its normal operational mode, the output processor providing, a sensor output signal indicative of one or more characteristics of the article.
地址 Worcester MA US