| 摘要 |
<p>PURPOSE:To obtain a sufficient operation margin which can greatly shorten the delay of a signal propagation time even at the time of bus isolation by providing a latch circuit which operates in synchronism with an internal clock. CONSTITUTION:The latch circuit 10 which operates in synchronism with the internal clock is provided on a signal line 4 which transmits an external signal. When a bus isolation control signal is inputted through a signal line 8, buffers 7, 7 are put in operation and buffers 5 and 5 are turned off; and external signals which are inputted through signal lines 4, 4 are latched by latch circuits 10, 10 and then outputted to internal buses 6, 6 through the latch circuits 10, 10 and buffers 7, 7 at the rising timing and falling timing of the internal clock from the internal clock line 11. Further, signals from a CPU 2 which are inputted through signal lines 3, 3 are cut off by the buffers 5, 5 and never outputted to internal buses 6, 6.</p> |
