| 摘要 |
PROBLEM TO BE SOLVED: To reduce a layout area by improving a write address generator performing complicated controls while using many gates. SOLUTION: In a FIFO semiconductor memory, a memory core RAMCORE is constituted of a memory array (MARRAY), a write address generator (WAG), valid bits (VB), write buffers (WDBV, WDB0, WDB1), sense amplifiers (SAV, SA0, SA1) and a read control (RCTL). The MARRAY is constituted of m words×n bits×2 having 1W1R cells and the VB is constituted of m words×2 bits having 1W1R cells. The WAG is constituted of shift registers and the WDBV is a write buffer for valid and the read control RCTL judges the effectiveness of read data.
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