| 摘要 |
A processor (100) is provided with a datapath and control logic, where the datapath (102) and/or the control logic (104) are constituted with basic execution blocks (BEB) (200). Each BEB includes an addressable storage and an arithmetic logic unit (ALU) (146) selectably coupled to each other in a manner that allows instruction execution and/or control decisions to be effectuated through storage read/write operations against the addressable storage and ALU operations performed by the ALU. In one embodiment, the addressable storage of each BEB is a cache memory (172). In another embodiment, the read, write and ALU operations are hierarchically organized.
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