Active clamps for multi-stage amplifiers in over/under-voltage condition

摘要

Multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients are presented. A multi-stage amplifier, having a differential amplification stage configured to provide a stage output voltage at an output node, based on a first input voltage and a second input voltage is presented. Furthermore, the multi-stage amplifier comprises a second amplification stage comprising an amplifier current source configured to provide an amplifier current; and an amplifier transistor arranged in series with the amplifier current source; wherein a gate of the amplifier transistor is coupled to the output node of the differential amplification stage. In addition, the multi-stage amplifier comprises a detection circuit.

主权项

1. A multi-stage amplifier comprising
a differential amplification stage configured to provide a stage output voltage at an output node, based on a first input voltage at a first input node and a second input voltage at a second input node; wherein the differential amplification stage comprises a first input transistor and a second input transistor forming a differential pair, wherein a gate of the first input transistor forms the first input node for receiving the first input voltage; wherein a gate of the second input transistor forms the second input node for receiving the second input voltage; and wherein an output node of the second input transistor forms the output node of the differential amplification stage; a second amplification stage comprising
an amplifier current source configured to provide an amplifier current; andan amplifier transistor arranged in series with the amplifier current source; wherein a gate of the amplifier transistor is coupled to the output node of the differential amplification stage; and a detection circuit comprising
a detection current source configured to provide a detection current;a detection transistor arranged in series with the detection current source; wherein a gate of the detection transistor is coupled to the output node of the differential amplification stage; wherein a mid-point between the detection current source and an input node of the detection transistor forms a sensing point; anda clamping transistor arranged in parallel to the first or the second input transistor; wherein a gate of the clamping transistor is coupled to the sensing point; wherein the detection circuit is configured such that the sensing point changes from a default state to a detection state, subject to the stage output voltage at the output node deviating from a default voltage by at least a pre-determined threshold value.