Digital class-D amplifier and digital signal processing method

摘要

A digital class D amplifier (10) is disclosed, comprising a pulse width modulator (PW Mod) comprising: a digital loop filter (Loop F) adapted to receive an input signal (x[n]) and a feedback signal (fb[n]), the digital loop filter (Loop_F) being adapted to process at a clock frequency (f_s) said input and feedback signals for providing as output a filtered digital signal (w[n]); a PWM conversion module (PW_CM) having an input (24) for receiving the filtered digital signal (w[n]) and having a first output (25) connected to the digital loop filter (Loop F), the PWM conversion module being adapted for processing the filtered digital signal (w[n]) and providing at said first output (25) the feedback signal (fb[n]). The PWM conversion module (PW_CM) comprises: a first comparator (CMP_N) adapted to compare the filtered digital signal (w[n]) with a first reference triangular waveform (VTn[n]) for providing as output a first PWM signal (yn[n]), the first reference triangular waveform having a frequency (f_osc) much lower than said clock frequency (f.s); a second comparator (CMP_P) adapted to compare the filtered digital signal (w[n]) with a second reference triangular waveform (VTp[n]) for providing as output a second PWM signal (yp[n]), the second reference triangular waveform (VTp[n]) being the inverse of the first triangular waveform (VTn[n]), said first (yn[n]) and second (yp[n]) PWM signals representing a differential output pulse width modulated signal (yn[n],yp[n]).

主权项

1. A digital class D amplifier comprising a pulse width modulator (PWM) comprising:
a digital loop filter having a first input configured to receive an input signal and a second input configured to receive a feedback signal, the digital loop filter configured to process, at a clock frequency, the input and feedback signals to output a filtered digital signal; and a PWM conversion module having an input for receiving the filtered digital signal and having a first output connected to the second input of the digital loop filter, the PWM conversion module configured to process the filtered digital signal and provide at the first output the feedback signal, said PWM conversion module comprising:
a first comparator configured to compare the filtered digital signal with a first reference triangular waveform to provide a first PWM signal, the first reference triangular waveform having a frequency substantially lower than the clock frequency;a second comparator configured to compare the filtered digital signal with a second reference triangular waveform to provide a second PWM signal, the second reference triangular waveform being the inverse of the first triangular waveform, and the first and second PWM signals representing in their combination a differential output pulse width modulated signal; andan algebraic adder having a first input coupled to an output of the first comparator and a second input coupled to an output of the second comparator, the algebraic adder configured to combine the first and said second PWM signals to provide the feedback signal.