发明名称 |
Apparatus and method for decoding digital data |
摘要 |
<p>The present invention relates generally to an improved decoder circuit used for decoding Reed-Solomon or BCH codes. According to one aspect of the invention, a step of performing solving an error locator polynomial is performed concurrently with a step of computing an error pattern. In particular, a decoder is provided which performs concurrent execution of a Chien search that determines the error locator polynomial for a received code word and a Forney algorithm that computes the error pattern. <IMAGE></p> |
申请公布号 |
EP1102406(A2) |
申请公布日期 |
2001.05.23 |
申请号 |
EP20000309609 |
申请日期 |
2000.10.31 |
申请人 |
STMICROELECTRONICS, INC. |
发明人 |
YANG, HONDA;GILL, JOHN T., III |
分类号 |
G06F11/10;H03M13/15;(IPC1-7):H03M13/15 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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