| 摘要 |
A data transfer system and a data processing apparatus are provided to improve data transfer rate without speeding up the clock speed and increasing the number of data signal lines. A data transmitter(10) transmits a second clock signal generated by dividing a first clock signal and a data signal comprising two bits every one cycle of the second clock signal. A data receiver(20) receives the second clock signal and the data signal, and detects the two bits contained in the data signal every one cycle of the second clock signal. A clock frequency of the second clock signal is a half of the clock frequency of the first clock signal. In the data signal, one bit is respectively allocated to a high interval and a low interval of one cycle in the second clock signal.
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