| 摘要 |
PROBLEM TO BE SOLVED: To provide a trench type insulated gate MOS semiconductor device having low on-resistance, large current density and large breakdown resistance in avalanche breakdown, and suppressing a bouncing voltage in turning off. SOLUTION: In this vertical and trench type insulated gate MOS semiconductor device, surfaces of p-type base regions 12 and surfaces of an n-type semiconductor substrates 11 are alternately repeatedly arranged between a plurality of trenches 13 having a plurality of linear parallel surface patterns along the longitudinal direction of the trenches 13. The trench type insulated gate MOS semiconductor device is provided with: a first inter-trench surface region where an emitter electrode 19 comes into common electrical contact with both surfaces of n-type emitter regions 16 and p+ -type body regions 17 in the p-type base regions 12 surfaces; and a second inter-trench surface region where either of the p-type base region 12 surfaces and the n-type semiconductor 11 surfaces occupy a surface extending along the longitudinal direction of the trenches 13. COPYRIGHT: (C)2009,JPO&INPIT |
