发明名称 CLOCK PULSE GENERATING CIRCUIT
摘要 PURPOSE:To decrease error at switching and to continue reduction of influence of instantaneous power failure and so on by providing a frequency dividing means of commercial frequency, a crystal oscillating frequency dividing means, a power failure detection means, a gate pulse generating mans, a judgement means, a synchronization controlling means and the like. CONSTITUTION:A frequency dividing circuit 3 of commercial frequency frequency- divides rectangular waves of the commercial frequency signal being output from a wave shaping circuit 2 by a frequency dividing number directed by direction signal SEL of commercial frequency zone, and then outputs completion signal of frequency dividing. A crystal oscillation frequency dividing circuit 5 frequency-divides crystal oscillation frequency signal being output from a crystal oscillation circuit 4, upto the same cycle as the completion signal of frequency dividing which is obtained by frequency dividing of the commercial frequency signal at the circuit 3, and then outputs the frequency divided signal as clock pulse signal TP. A cycling circuit 8 receives power failure signal, and so on, from a power failure detection circuit 7, the circuit 3 and the circuit 5, and thereafter compares the completion signal of frequency dividing from the circuit 3, with the gate pulse of a gate circuit 6 when electric power is conducted, and then outputs reset signal of the circuit 3 in case the completion signal of frequency dividing still remains in and out side the gate pulse.
申请公布号 JPH0460493(A) 申请公布日期 1992.02.26
申请号 JP19900170214 申请日期 1990.06.29
申请人 TOSHIBA CORP 发明人 MATSUNO YOSHIAKI
分类号 H03L7/00;G04G3/00 主分类号 H03L7/00
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