THREE PORT SRAM BIT CELLS WITH FIRST AND SECOND READ WORDLINE AND WRITE WORDLINE ON DIFFERENT METAL LAYERS AND ASSOCIATED LANDING PADS SPLIT ACROSS BOUNDARY EDGES OF EACH SRAM BIT CELL

摘要

Static random access memory (SRAM) bit cells with wordline landing pads (312(1), 312(2), 312(3)) are split across boundary edges of the SRAM bit cells are disclosed. In one aspect, an SRAM bit cell is disclosed employing write wordline (302) in a second metal layer (M2), first read wordline (304) in third metal layer (M4), and second read wordline (306) in fourth metal layer (M4). Employing wordlines in separate metal layers allows wordlines to have wider widths, which decrease wordline resistance, decrease access time, and increase performance of SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks inside and outside of a boundary edge of the SRAM bit cell. Landing pads corresponding to the write wordline are placed on corresponding tracks within the boundary edge of the SRAM bit cell.