发明名称 |
Mechanism for preventing radiation induced latch-up in CMOS integrated circuits |
摘要 |
A CMOS circuit formed in a semiconductor substrate having improved immunity to radiation induced latch-up and improved immunity to a single event upset. The circuit architecture of the present invention can be utilized with N-Well, P-Well and dual Well processes. For example, the circuit is described relative to an N-Well process. An N-Well is formed in a p-type substrate. A network of p-channel transistors are formed in the N-Well and a network of n-channel transistors are formed in the p-type substrate. A continuous P+guard ring is formed surrounding the n-channel transistors and between the n-channel transistors and the N-Well. Similarly, a continuous N+guard ring is formed surrounding the p-channel transistors and between the p-channel transistors and the p-type substrate. In the event of a radiation hit, the guard rings operate to reduce the parasitic impedance in the collector circuits of the parasitic bipolars forming a parasitic SCR and also act as additional collectors of radiation induced current. Single event upset immunity is improved by forming duplicate functions in an n-channel network and a p-channel network. N-channel control transistors are coupled to control p-channel load transistors and p-channel control transistors are coupled to control n-channel load transistors.
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申请公布号 |
US5406513(A) |
申请公布日期 |
1995.04.11 |
申请号 |
US19930014319 |
申请日期 |
1993.02.05 |
申请人 |
THE UNIVERSITY OF NEW MEXICO |
发明人 |
CANARIS, JOHN;WHITAKER, STERLING;CAMERON, KELLY |
分类号 |
G11C5/00;G11C11/412;H01L27/092;(IPC1-7):G11C11/40 |
主分类号 |
G11C5/00 |
代理机构 |
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