| 摘要 |
PROBLEM TO BE SOLVED: To reduce failure analysis time.SOLUTION: A semiconductor integrated circuit device according to one embodiment comprises: a MOSFET m1 connected to a word line WL of a memory cell array 10; and an OR logic gate g1 connected to the MOSFET m1. The OR logic gate g1 includes a first input terminal to which a low power consumption mode control signal n2 is inputted, a second input terminal to which an analysis control signal n3 is inputted, and an output terminal connected to a gate of the MOSFET m1. The semiconductor integrated circuit device is brought into an analysis state when the analysis control signal n3 is at H-level.SELECTED DRAWING: Figure 4 |
