发明名称 CLOCK GENERATION CIRCUIT
摘要 PURPOSE:To provide a function to start the supply of an internal clock from a specific phase, a function to stop the supply at the specific phase, and a function to restart the supply from the specific phase. CONSTITUTION:A PLL circuit 1 is provided with the frequency of two times the frequency of a reference clock signal 40 supplied from the outside, and generates an original clock signal 30 synchronized with the clock signal. A timer circuit 2 counts the pulse of the reference clock signal 40 so as to measure a time equivalent to the lock-in time of the PLL circuit 1, and outputs a count completion signal 60 when a count value arrives at a prescribed value. A start control circuit 3 controls a clock buffer circuit 5 so as to start to supply the original clock signal 30 as the internal clock signal 34 synchronizing with the reference clock signal 40 after the output of the count completion signal 60 is issued. When a clock stoppage request signal 42 is asserted, a stop control circuit 4 controls the clock buffer circuit 5 so as to stop the supply of the internal clock signal 34 synchronizing with the reference clock signal 40.
申请公布号 JPH0685663(A) 申请公布日期 1994.03.25
申请号 JP19930109476 申请日期 1993.05.11
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NISHIMICHI YOSHIHITO
分类号 G06F1/12;G06F1/04;H03L3/00;H03L7/00;H03L7/08 主分类号 G06F1/12
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