| 摘要 |
Data processing apparatus, in which at least a first and a second data handling node are connected to a common data bus, comprises an arbitration circuit, responsive to requests for control of the data bus from the data handling nodes, for allocating control of the data bus to selected ones of the data handling nodes for successive access periods of a predetermined length. The first data handling node comprises a processor for requesting control of the data bus for one access period in order to transmit a data request to the second data handling node, and the second data handling node comprises a processor, responsive to a data request received from the first data handling node, for requesting control of the data bus for a subsequent access period to transmit the requested data to the first data handling node. Data requests and the subsequent transmission of the requested data are thus treated as two separate bus transactions, each transaction taking place during an access period of a predetermined length.
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