Self-timed low power ratio-logic system having an input sensing circuit

摘要

A ratio-logic system having an input sensing device and a resetable delay device is disclosed. The input sensing device receives an input having a first logic state and a second input having a second logic state. The input sensing device then asynchronously outputs a first state-change signal if the first logic state differs from the logic state of a previous input, and a second state-change signal if the second logic state differs from the first logic state. The resetable delay device receives the first and second state-change signals and asynchronously outputs a power-up signal to a ratio-logic device for a predetermined amount of time after the first state-change signal is received. The resetable delay device then powers-down the ratio-logic device after the predetermined amount of time is over. The predetermined amount of time is reset if the input sensing device receives the second state-change signal before the predetermined amount of time is over.